PMOS Input buffer compatible with logic inputs from an NMOS microprocessor

ABSTRACT

A PMOS input buffer compatible with logic voltage levels provided by NMOS or TTL microprocessor means uses a limited number of transistors of limited size for driving a load in response to such logic and is adapted for use under widely varying operating conditions.

BACKGROUND OF THE INVENTION

The field of this invention is that of metal-oxide-semiconductor (MOS)integrated circuits, and the invention relates more particularly to animproved MOS input buffer for use in such a circuit.

Microprocessors implemented in NMOS integrated circuit technology aretypically proposed for use in automotive control applications to meetthe speed, complexity and cost requirements of such applications.However the LED or vacuum fluorescent display means and PMOS displaydriver means which are usually proposed for use in such automotiveapplications to meet the requirements of cost and sunlight conditionsand the like have input requirements which are typically not compatiblewith the voltage levels of the logic signals provided by such NMOSmicroprocessor means. That is, conventional input buffer means are notadapted for use between the NMOS microprocessor and the associated PMOScircuit means. For example, the input signals provided by the NMOSmicroprocessor are referenced to the drain supply voltage so that aconventional input buffer utilizing a grounded source enhancement deviceand a saturated load with the Beta ratio adjusted for input voltagelevels is found to be inappropriate. Similarly, known input buffer meansutilizing differential amplifier means are found to provide very littlegain and are also considered inappropriate. Accordingly relativelyexpensive CMOS buffer means and the like have been proposed for use topermit the preferred microprocessor, display, and driver means to beemployed together in automotive control applications.

SUMMARY OF THE INVENTION

It is an object of this invention to provide a novel and improvedintegrated circuit means for use between NMOS integrated circuit meansand cooperating integrated circuit means implemented in other than NMOScircuit technology; to provide a novel and improved input buffer for usebetween NMOS microprocessor means and integrated circuit means includingPMOS display driver means and the like; and to provide an improved inputbuffer compatible with logic inputs from NMOS and TTL microprocessormeans which is characterized by low cost, by the use of a limited numberof transistor means of relatively limited size, and by being adapted foruse under the widely varying operating conditions typically associatedwith automotive control applications and the like.

Briefly described, the novel and improved integrated circuit of thisinvention comprises input buffer means implemented in PMOS integratedcircuit technology to be compatible with the output voltage levels oflogic signals provided by NMOS microprocessor means. The improved PMOSinput buffer includes level-shifting means responsive to the logicsignals provided by the NMOS microprocessor means for providingcorresponding logic signals at substantially improved voltage levels.Preferably the level shifting means are selected to be dependent on thelevel of the drain supply voltage provided in the input buffer forassuring that the desired level shifting is achieved during variationsin drain supply voltage under widely varying operating conditions suchas might be encountered in automotive control applications. The improvedinput buffer further includes Schmitt trigger means arranged to beresponsive to the levelshifted input signals to provide desiredhysteresis for improving noise suppression in the buffer. Preferably theSchmitt trigger means are arranged so that the thresholds of the triggertrack the outputs of the level shifting means over the range ofvariation in the drain supply voltage of the buffer system. In thepreferred embodiment of the invention, the output stages of the bufferinclude source follower means and the Schmitt trigger is arranged to bedriven by the source follower means for achieving further improved speedcharacteristics in the buffer. The source follower means also serves toprovide current gain and improved level shifting and in the preferredembodiment of this invention, the input buffer further includes anotherwise conventional push-pull output stage for achieving furtherdesired current gain.

DESCRIPTION OF THE DRAWINGS

Other objects, advantages and details of the novel and improved inputbuffer of this invention appear in the following detailed description ofpreferred embodiments of the invention, the detailed descriptionreferring to the drawings in which:

FIG. 1 is a schematic circuit diagram of a PMOS input buffer provided bythis invention; and

FIG. 2 is a graph illustrating operating characteristics of the inputbuffer of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to the drawings, the novel and improved MOS integrated circuitof this invention is shown to comprise an input buffer 10 having voltagelevel shifting means 12 incorporated MOS transistors M₁ -M₆. All PMOStransistors are illustrated in FIG. 1 but it should be understood thatother circuit components can also be incorporated in the improved inputbuffer 10 within the scope of this invention. The channels of thetransistors M₂ and M₁ are connected in series between the source anddrain supply voltages V_(ss) and V_(dd). In the preferred embodiment,both transistors are depletion-type devices which are always on and thedrain of transistor M₂ is connected to the source of transistor M₁ toform the node N₁ as illustrated in FIG. 1. The gates of transistors M₁and M₂ are connected to the drain supply voltage and to the sourcesupply voltage respectively, preferably through respective currentlimiting resistors 14 and 16 which serve to protect the input bufferagainst static electricity. The transistor M₁ is operated in the trioderegion to serve as a resistor and transistor M₂ is always saturated toserve as a current source.

The channels of transistors M₄ and M₃ are also connected in seriesbetween the source and drain supply voltages. The gate of transistor M₃is connected to node N₁. The drain of transistor M₄ is connected to thesource of transistor M₃ to form the node N₂ as shown in FIG. 1 and thatnode N₂ is connected to the gate of transistor M₄. Both of thetransistors M₃ and M₄ are enhancement-type devices and are proportionedand arranged so that they are always on to provide a relatively limitedlevel of current. The channels of transistors M₆ and M₅ are alsoconnected in series between the source and drain supply voltages, bothof those transistors being enhancement-type devices. The gate oftransistor M₅ is connected to the input 18 of the buffer which istypically provided by an NMOS microprocessor or atransistor-transistor-logic (TTL) circuit or the like. The gate of thetransistor M₆ is connected to the node N₂ in common with the gate oftransistor M₄ so that transistors M₄ and M₆ form a current mirror. Thedrain of transistor M₆ is connected to the source of transistor M₅ toform node N₃ as is shown in FIG. 1. Transistors M.sub. 3 -M₆ all operatein the saturation region.

In accordance with this invention, the level shifting means 12cooperates with Schmitt trigger means 20 comprising the PMOS transistorsM₇ -M₁₂ and M₁₇ which provides the input buffer 10 with desiredhysteresis. That is, the channels of transistors M₁₀ and M₉ areconnected in series between the source and drain supply voltages asshown in FIG. 1. The gates of the transistors M₉ and M₁₀ are connectedto the drain and source supply voltages respectively, preferably througha respective current limiting resistors 22 and 24 for protecting theinput buffer against static electricity. The transistor M₉ is anenhancement-type device and transistors M₁₀ and are depletion-typedevices and the drain of M₁₀ is connected to the source of M₉ to formthe node N₅. Transistor M₁₇ has its drain and gate connected to node N₅and its source connected to V_(ss). The channels of transistors M₇ andM₈ are connected in series between the drain supply voltage V_(dd) andnode N₅ and the channels of transistors M₁₁ and M₁₂ are also connectedin series between the drain supply voltage and node N₅. Transistor M₇has its gate connected to its source and is also connected to the drainof transistor M₈ to form node N₄. The gate of transistor M₈ is connectedto node N₃. Transistor M₁₁ has its gate connected to its source and isalso connected to the drain of transistor M₁₂ to form node N₆. Thetransistors M₇, M₁₀, M₁₁ and M₁₇ are depletion-type devices whiletransistors M₈, M₉ and M₁₂ are enhancement devices. Transistors M₇ andM₁₁ are saturated while transistor M₁₀ and M₁₇ operate in the linearregion.

In accordance with this invention, the input buffer 10 further includesthe driver means 26 which preferably includes source follower, buffermeans 28 comprising the transistors M₁₃ and M₁₄. The driver alsoincludes an output stage 30 comprising the transistors M₁₅ and M₁₆.Preferably, the channels of transistors M₁₄ and M₁₃ are connected inseries between the source and drain supply voltages. The drain ofdepletion device M₁₄ is connected to the source of enhancement deviceM₁₃ to form the node N₇ which is connected in common to the gate oftransistor M₁₂ in the Schmitt trigger 20. The gate of transistor M₁₄ isconnected to the source supply voltage, preferably through the staticprotection resistor 24 and the gate of transistor M₁₃ is connected tonode N₄ in the Schmitt trigger. The two enhancement-type transistors M₁₆and M₁₅ are connected in push-pull configuration between the source anddrain supply voltages and the drain of transistor M₁₆ is connected tothe source of transistor M₁₅ to form the output 34 of the buffer 10. Thegate of transistor M₁₆ is connected to the node N₇ and the gate oftransistor M₁₅ is connected to the node N₆ in the Schmitt trigger 20.

As thus far described, the input buffer 10 is preferably arranged in anintegrated circuit to receive logic signals from an NMOS microprocessoror the like. In a preferred embodiment of the invention where the bufferis used for driving PMOS circuit means including LED or vacuumfluorescent display means in an automotive control application forexample, the source supply voltage V_(ss) corresponds to the vehiclesupply voltage and typically varies from -8 to -18 volts over an ambienttemperature (t_(a)) range of -30° C. to 85° C. and is typically about9.5 v. The drain supply voltage V_(dd) corresponds to system ground. Inthat arrangement, voltages at input 18 representing logic inputs "0" and"1" will be within a short range of V_(dd), typically in a range fromV_(dd) +0.8 v. to V_(dd) +3.5 v. and neither input will approach V_(ss).

In one preferred embodiment of the invention, the PMOS transistors M₁-M₁₇ have widths and lengths (W/L) in mils as set forth in Table Ibelow:

                  TABLE I                                                         ______________________________________                                        Transistor                                                                              W/L          Transistor                                                                              W/L                                          ______________________________________                                        M.sub.1   .3/1.0       M.sub.9    .3/2.4                                      M.sub.2   .3/.60       M.sub.10   .7/.6                                       M.sub.3   .3/1.0       M.sub.11  .35/.6                                       M.sub.4   18.0/.60     M.sub.12  3.4/.3                                       M.sub.5   .3/1.0       M.sub.13  1.2/.3                                       M.sub.6   18.0/.60     M.sub.14   .3/1.0                                      M.sub.7   .3/1.0       M.sub.15  1.0/.3                                       M.sub.8   1.4/.3       M.sub.16  1.0/.3                                                              M.sub.17   .7/.6                                       ______________________________________                                    

With those characteristics, the input buffer 10 has the following inputspecifications:

    ______________________________________                                                     Min.     Max.                                                    ______________________________________                                        (1) V.sub.ss    8 volts   18 volts                                            (2) t.sub.a   -30° C.                                                                            85° C.                                       (3) V.sub.IH   3.5 volts  V.sub.ss plus .3 volts                              (4) V.sub.IL  -.3 volts    .8 volts                                           (5) Hysteresis                                                                               .5 volts    .8 volts                                           ______________________________________                                         (voltages stated with respect to V.sub.dd)                               

That is, where the source supply voltage varies from 8 to 18 volts, theinput buffer is adapted to be responsive to logic high input voltagesvarying from 3.5 volts to V_(ss) +0.3 volts and to logic low inputvoltages varying from -0.3 volts to 0.8 volts while providing desiredhysteresis of 0.5 volts.

As thus described, the buffer 10 provides level shifting, voltage andcurrent gain, and desired hysteresis corresponding to the inputspecification as set forth above. In the level-shifting means 12, thetransistor M₂ is always saturated and serves as a current source whilethe transistor M₁ operates in the triode region and serves as aresistor, whereby a constant reference voltage V_(REF) is generated atnode N₁, that voltage being referenced to V_(ss). The voltage V_(REF)corresponds generally to the drain to source voltage across transistorM₁ and varies with V_(ss) such that as V_(ss) varies between -8 and -18volts, the reference voltage V_(REF) varies between 3 volts and 4 volts.That voltage at N₁ then serves to set the gate voltage at transistor M₃to provide the desired voltage level shifting. That is, the currentI_(M3) in transistor M₃ equals current I_(M4) in transistor M₄ ; thecurrent I_(M5) in transistor M₅ equals current I_(M6) in transistor M₆ ;the current I_(M4) equals the current I_(M6) ; and the voltage at nodeN₂ corresponds to the threshold voltage V_(T) of transistor M₄. Thevoltage at node N₃ therefore corresponds generally to the input voltageat 18 less the reference voltage V_(REF) plus the noted thresholdvoltage V_(T). The transistors M₃ -M₆ all operate in the saturationregion since their gate voltages never exceed the drain supply voltageV_(dd). In that arrangement, where the reference voltage V_(REF) is setto correspond to V_(IH), at 3.5 volts as set out in specification (3),the gate voltages provided at node N₃ have logic levels of V_(T) andV_(T) +(V_(IH) (min.)-V_(IL) (max.)) which is ideal to drive the Schmitttrigger stage of the buffer as is illustrated in FIG. 2. That is, thelow and high logic voltage levels L₃ and H₃ appearing at node N₃ asvoltages V_(IL) 0.8 volts) and V_(IH) (3.5 volts) are applied at theinput 18 respectively result in a minimum output of the level shiftingmeans 12 as indicated by curves L₃ and H₃ in FIG. 2 as the drain supplyvoltage V_(dd) varies between -8 and -18 volts.

In accordance with this invention, the Schmitt trigger means 20 isfurther adapted to cooperate with the level-shifting means 12 to assureproper operation of the buffer 10 over a wide range of operatingconditions. Thus the thresholds V_(TH) + and V_(TH) - of the Schmitttrigger are described by the following expressions:

(1) V_(TH) +≅(I_(M7) +I_(M11))R+V_(TM).sbsb.8 ; and

(2) V_(TH) -≅I_(M7) R+V_(TM).sbsb.8

where I_(M7), I_(M10) and I_(M11) are the currents in transistors M₇,M₁₀ and M₁₁ respectively, R is a resistance across the parallelcombination of transistors M₁₀ and M₁₇, and V_(TM8) is the thresholdvoltage of transistor M₈. In that regard, the transistors M₇ and M₁₁,are saturated and transistors M₁₀ and M₁₇ operate in the linear region.The hysteresis provided by the Schmitt trigger corresponds to I_(M11) R.

In that arrangement, transistors M₇ and M₈ form a first leg of theSchmitt trigger and transistors M₁₁ and M₁₂ form the second or alternateleg of the trigger which cooperate with transistors M₁₀ and M₁₇ toprovide the trigger with selected hysteresis. The transistor M₉ thenacts as a resistor to the drain supply voltage and adds some dependenceon drain supply voltage to both of the thresholds of the Schmitt triggerwithout affecting the hysteresis provided by the Schmitt trigger fornoise suppression purposes. In that way, the Schmitt trigger compensatesto some extent for the V_(dd) dependence of the voltage at node N₁ (dueto the body effect of transistors M₁ and M₅) as previously described. Asa result, the thresholds of the Schmitt trigger in the buffer 10 trackthe output of the level shifting means 12 over the range of variation ofthe drain supply voltage as is indicated at V_(TH) + and V_(TH) - inFIG. 2.

The final output stage 26 of the buffer 10 then cooperates with theSchmitt trigger 20 in providing desired output voltage and drive currentcapabilities as will be understood. That is, the transistors M₁₃ and M₁₄serve as a source follower to provide current gain and some additionalshift of voltage level at node N₇. The fairly large transistor M₁₂ inthe Schmitt trigger is then driven by the source follower as illustratedin FIG. 1 to improve the propogation delay achieved by the Schmitttrigger. The transistors M₁₅ and M₁₆ are arranged in push-pullconfiguration as shown and comprise a conventional buffer output stage.

As thus described, the buffer 10 provides A.C. propagation delay (V_(IN)to V_(OUT)) as illustrated in Table II:

                  TABLE II                                                        ______________________________________                                        Output         V.sub.ss = -8 v.                                                                           V.sub.ss = -18 v.                                 Condition                                                                             Transition 1→0                                                                            0→1                                                                           1→0                                                                          0→1                            ______________________________________                                        Typical        295     195      335   235                                     Worst          655     715      575   475                                     Case                                                                          ______________________________________                                    

The data is given in nanoseconds for operation at 120° C. in both casesfor the case where 1=V_(ss) and 0=V_(dd).

In use, the buffer 10 typically receives a logic input from an NMOSmicroprocessor or the like so that the input voltage V_(IN) at 18 varieswithin a short range of the drain supply voltage V_(dd) and does notapproach the level of the source supply voltage V_(ss). The buffer 10 iscompatible with such an input from the microprocessor and serves as anoninverting input buffer to provide desired voltage and current levelsfor driving circuits including PMOS display driver means and the like inautomotive applications.

In that regard, transistors M₁ and M₂ are always on and serve as avoltage divider to provide a reference voltage V_(REF) at node N₁. Thatreference voltage varies in the range from 3 volts to 4 volts as thedrain supply voltage V_(ss) varies from -8 to -18 volts and the voltageat N₁ biases the level shifting components M₃ -M₆ to provide desirablylevel-shifted voltages at node N₃. That is, the transistor M₃ has thesame size and resistance as transistor M₅ and transistor M₄ has the samesize and resistance as transistor M₆. Transistors M₄ and M₆ form acurrent mirror. Transistor M₃ is biased by reference voltage V_(REF) andserves as a voltage-to-current converter tending to provide a desiredcurrent level in transistor M₄ and therefore in transistor M₆. In thatarrangement, as the input voltage V_(IN) varies as above described, thevoltage across transistor M₅ corresponds to the voltage acrosstransistor M₃ and produces a desired level-shifting of the low and highvoltages at node N₃ away from V_(dd) toward V_(ss) as is indicated bycurves L₃ and H₃ in FIG. 2. Those voltage levels at N₃ then cooperatewith the Schmitt trigger 20 and with the driver means 26 to provide anoutput 34 at desired voltage and current levels and with desiredhysteresis for noise suppression purposes for driving the notedautomotive control circuit.

For example, when the input voltage V_(IN) at 18 is high correspondingto a logic input "1" nearer to V_(ss), the voltage at node N₃corresponds to curve H₃ in FIG. 2 so that the transistor M₈ is turnedoff. When M₈ turns off, the voltage at N₄ moves toward the level of thedrain supply voltage V_(dd). Transistors M₁₃ and M₁₄ form a sourcefollower and as the voltage at N₄ goes toward V_(dd), transistor M₁₃conducts and the voltage at node N₇ also goes close to V_(dd) (nearlogic "0"). Transistor M₁₆ is therefore turned on and the voltage atoutput 34 also goes high nearer to V_(ss).

The transistors M₉ and M₁₀ are always on in the Schmitt trigger 20 andthe transistor M₁₀ operates in the triode region to function as aresistor. There is accordingly a small current flowing in transistors M₉and M₁₀ and M₉ applies a selected voltage bias to node N₅. Beforetransistor M₈ is turned off as noted above, a small current also flowsin transistor M₇ and M₈ providing additional voltage at the node N₅ aswill be understood. Then, when transistor M₁₂ is turned on as notedabove, transistor M₁₁ has slightly less resistance than transistor M₇and provides a positive feedback so that the voltage at node N₅ goesslightly toward V_(dd), thereby turning transistor M₈ off morecompletely to provide the desired minimum 0.5 volt hysteresis asrequired by specification (5) noted above.

Conversely when the input voltage V_(IN) at 18 goes low corresponding tologic input "0" nearer to V_(dd), the voltage at node N₃ corresponds tocurve L₃ in FIG. 2 so that the transistor M₈ is turned on and currentagain flows in transistor M₇. The voltage at node N₄ goes toward V_(ss)so that transistor M₁₃ is also turned off and the voltage at node N₇also moves toward V_(ss). That voltage at N₇ then turns off transistorM₁₂ and also turns off transistor M₁₆ so that the voltage at output 34goes toward V_(dd). As transistor M₁₂ is turned off, the current at nodeN₅ decreases and voltage at node N₅ decreases, The voltage at node N₆also goes toward V_(dd) and transistor M₁₁ stops conducting becausethere is no voltage across the transistor. As thus described, nodes N₄and N₆ are both outputs from the Schmitt trigger. The inverted outputfrom node N₄ is buffered through the source follower stage formed bytransistors M₁₃ and M₁₄ and provides desired current gain while alsocooperating with the noninverted output from node N₆ in operating thefinal output stage of the buffer 10 as formed by the transistors M₁₅ andM₁₆.

In that way the input buffer 10 accomplishes the desired results andmeets the desired input buffer specification utilizing a limited numberof PMOS transistors of relatively limited size.

It should be understood that although particular embodiments of theimproved input buffer of this invention have been described above by wayof illustrating the invention, this invention includes all modificationsand equivalents of the disclosed embodiments falling within the scope ofthe appended claims.

I claim:
 1. An input buffer comprising means responsive to logic inputsignals at selected voltage levels for providing corresponding controlsignals at level-shifted voltage levels, Schmitt trigger meansresponsive to said control signals for providing corresponding triggeroutput signals with selected hysteresis, and output means responsive tosaid trigger signals for providing buffer output signals having improvedcompatibility for driving selected circuit means, said level-shiftingmeans comprising MOS transistor means forming voltage divider means forproviding a reference voltage at a selected level, a pair of MOStransistor means forming a current mirror means, MOS transistor meansbiased by said reference voltage to provide desired current levels inone of said current mirror transistor means, and additional MOStransistor means responsive to said logic input signals and to saidcurrent mirror means for assuring said corresponding control signals areprovided at desired level-shifted voltage levels.
 2. An input buffercomprising means responsive to logic input signals at selected voltagelevels for providing corresponding control signals at level-shiftedvoltage levels, Schmitt trigger means responsive to said control signalsfor providing corresponding trigger output signals with selectedhysteresis, and output means responsive to said trigger signals forproviding buffer output signals having improved compatibility fordriving selected circuit means, said Schmitt trigger means havingtransistor means therein arranged to define selected voltage thresholdsfor the trigger means and having an additional transistor meansconnected between said first named transistor means and a system supplyvoltage to add dependence on the system supply voltage to the triggerthresholds so that the threshold voltages of the trigger means tracksaid corresponding control signals furnished by the level-shifting meansfor providing said trigger output signals in response to control signalswithin the trigger thresholds during said supply voltage variations. 3.An MOS integrated circuit input buffer comprising PMOS integratedcircuit means responsive to logic input signals provided at voltagelevels corresponding to those provided by PMOS integrated circuit meansfor providing corresponding control signals at level-shifted voltagelevels, PMOS integrated circuit means forming Schmitt trigger meansresponsive to said level-shifted control signals for providingcorresponding trigger output signals with selected hysteresis, and PMOSintegrated circuit output means responsive to said trigger signals forproviding buffer output signals having improved compatibility fordriving PMOS integrated circuit means, said level-shifting meanscomprising MOS transistor means forming voltage divider means forproviding a reference voltage at a selected level, a pair of MOStransistor means forming a current mirror means, MOS transistor meansbiased by said reference voltage to provide desired current levels inone of said current mirror transistor means, and additional MOStransistor means responsive to said logic input signals and to saidcurrent mirror means for providing control signals corresponding to saidlogic input signals at level-shifted voltage levels.
 4. An MOSintegrated circuit input buffer as set forth in claim 3 wherein saidSchmitt trigger means comprises a pair of MOS transistor means arrangedin parallel and additional MOS transistor means arranged in first andalternate legs of the trigger means connected to said pair of paralleltransistor means to define selected voltage thresholds for the triggermeans and to be operable in response to said control signals within thetrigger thresholds for providing corresponding trigger output signalswith desired hysteresis, and has another MOS transistor means connectedbetween said parallel transistor means and a system supply voltage toadd dependence on the system supply voltage to the trigger thresholdsfor modifying the thresholds of the Schmitt trigger means to track saidcontrol signals during variations in said system supply voltage.
 5. AnMOS integrated circuit input buffer as set forth in claim 4 wherein saidoutput means includes push-pull driver means and said PMOS integratedcircuit means includes source follower means responsive to the signalsprovided by said above-named Schmitt trigger transistor means forproviding the trigger output signals with improved current gain andimproved propagations delay, said source follower means being arrangedto cooperate in driving said Schmitt trigger means for achievingimproved speed characteristics in the buffer.
 6. An input buffer systemcomprising means responsive to logic input signals at selected voltagelevels for providing corresponding control signals at level-shiftedvoltage levels, Schmitt trigger means responsive to said control signalsfor providing corresponding trigger output signals with selectedhysteresis, and output means responsive to said trigger signals forproviding buffer output signals having improved compatibility fordriving selected circuit means, said output means including push-pulldriver means and said system including source follower means responsiveto the signals provided by said above-named Schmitt trigger means forproviding the trigger output signals with improved current gain andimproved propagation delay, said source follower means being arranged tocooperate in driving said Schmitt trigger means for achieving improvedspeed characteristics in the input buffer system.